Defects (e. g. particles) can cause electrically measurable faults (killer defects) dependent on the chip layout and the defect size. These faults are responsible for manufacturing related malfunction of chips. So, defect density and size distributions are important for yield enhancement and to control quality of process steps and product chips, as described in Staper, C. H., Rosner, R. J., “Integrated Circuit Yield Management and Yield Analysis: Development and Implementation,” IEEE Transactions on Semiconductor Manufacturing, pp. 95–102, Vol. 8, No. 2, 1995.
Test structures are used to detect faults and to identify and localize defects. The double bridge test structure was proposed by Khare, et al., “Extraction of Defect Size Distributions in an IC Layer Using Test Structure Data,” IEEE Transactions on Semiconductor Manufacturing, pp. 354–368, Vol. 7, No. 3, 1994, to extract size distributions based on electrical measurements. This test structure design requires two conducting layer having different resistivity. Thus, this design requires at least one polysilicon layer and one metal layer. The Harp test structure was proposed by Hess, C., Weiland, L. H., “Harp Test Structure to Electrically Determine Size Distributions of Killer Defects,” IEEE Transactions on Semiconductor Manufacturing, pp. 194–203, Vol. 11, No. 2, 1998, which may be used for any kind of layers, but even the harp test structure requires at least two layers, which may slow down the data extraction procedure.
Parallel lines—each connected to two pads—are implemented inside a test structure to electrically determine a defect size distribution. If a defect occurs and causes an electrically measurable fault, either two or more test structure lines are shorted or one or more test structure lines are opened. The greater the number of test structure lines involved, the larger the defect that caused this measured fault.
FIG. 1 shows the principle design of such nested serpentine lines, which is based on a structure proposed by Glang, R., Defect Size Distribution in VLSI Chips, “IEEE Transactions on Semiconductor Manufacturing,” pp. 265–269, Vol. 4, No. 4, 1991. FIG. 1 shows a structure 100 having a plurality of nested serpentine lines 102a–102n, where n is the number of lines 102a–102n. Each line 102a–102n includes a pair of pads 104a–104n and 105a–105n, respectively. Thus, a pair of lines (e.g., 102a, 102b) requires four pads (e.g., 104a, 105a, 104b, 105b).
Glang used 5 serpentine lines within two combs, and implemented several structures having different dimensions to determine a defect size distribution by comparing the number of detected defects dependent on the dimension of the structures. Having a high number of nested serpentine lines enables the direct extraction of defect size distribution by comparing the number of detected defects dependent on the number of involved lines.
Each NEST structure is connected to a 2-by-N pad frame. FIG. 2 shows a complete NEST structure design, which was automatically generated in just a few seconds. This exemplary NEST structure 200 includes 3104 parallel lines in a single metal layer.
In a 2-by-N pad frame the number of pads is very limited. To enable the detection of opens and shorts, each test structure line is connected to two pads. So, only N/2 lines may be implemented; that does not fill a relatively large chip area that is sufficient to detect random defects. For this reason, the lines are designed as serpentines to fill the complete test chip area. Nevertheless, an improved structure allowing a larger number of lines is desired.